Based on this presentation some of those PAM5 codes (2 byte "SSD" and respectively 4 byte combo "csreset" and "ESD") mark the start and respectively end of frame, similar to how J/K and T/R do the same for 100BASE-TX.
The 802.3-2005 standard explains how these are coded relative to normal data:
During data encoding, PCS Transmit utilizes a three-state convolutional encoder. The transition from idle or carrier extension to data is signalled by inserting a SSD, and the end of transmission of data is signalled by an ESD. [...] During idle and carrier extension encoding, special code-groups with symbol values restricted to the set {2, 0, –2} are used. These
code-groups are also generated using the transmit side-stream scrambler. However, the encoding rules for the idle, SSD, and carrier extend code-groups are different from the encoding rules for data, CSReset, CSExtend,
and ESD code-groups. During idle, SSD, and carrier extension, the PCS Transmit function reverses the sign of the transmitted symbols. This allows, at the receiver, sequences of code-groups that represent data, CSReset, CSExtend, and ESD to be easily distinguished from sequences of code-groups that represent SSD,
carrier extension, and idle.
CSReset means "Convolutional State Reset" and SSD/ESD mean Start-of-Stream/End-of-Stream Delimiter.
The actual codes are publicly available [for free] as ASCII table 40-1 and table 40-2. The codes are given per byte there, e.g. to send SSD, you send SSD1 and SSD2 in this order.
