I understand the higher level of TCAM and how it differs from CAM and also RAM. My question is from the architectural point of view. I've read that TCAM search is really faster than RAM due to the parallelism, so TCAM can search for a content for the entire TCAM in parallel fashion in one clock cycle (which is why it is used in Routers). If this is correct, how is searching in RAM performed so I can compare between them?

Thank you.


The best scenario for a RAM search is that you have the data stored in a hash table, and you spend the cycles to calculate the hash, then you must go to that point in the table and read the value.

There are other RAM storage methods, but a full discussion of data structures and searching methods is beyond the scope of this site.


We are seeing less and less of ASIC's and more and more of general purpose CPU bcs of Moore's Law paired with economics and importantly power consumption.

TCAM is not the cure all for hardware search lookups. TCAM is power hungry, expensive and takes up quite a bit of silicon space. It would not be unusual for it to be the most expensive component on commodity switches. Many vendors use a blend of BCAM memory, SRAM, NPUs and software algorithms to perform ternary lookups (see MX trio chipset and EzChip NPUs in ASRs, Trie lookups). source


Generally speaking, CAM is often described as the opposite of random access memory (RAM). To retrieve data on RAM, the operating system (OS) must provide the memory address where the data is stored. Data stored on CAM can be accessed by performing a query for the content itself, and the memory retrieves the addresses where that data can be found. Due to its parallel nature, CAM (and by extension TCAM) is much faster than RAM. However, it is not widely used in most electronics because it is expensive to build, consumes a lot of power and generates a high level of heat that must be dissipated. source


Historically, Cisco networking devices ran Reduced Instruction Set Computing, RISC, processors. Meanwhile, Intel was selling its x86 Complex Instruction Set Computing, CISC, architecture. The horsepower appears low but the RISC model packs performance. Currently, Cisco uses a mixture of MIPS, PowerPC and x86, but it would like to standardize on one architecture, said Pradeep Kathail, a chief software architect at Cisco, speaking at an AppliedMicro press event at ARM TechCon. At present, classifying a processor as RISC or CISC is almost impossible, because their instructions sets all look similar now with parallel computing.

ARM Architecture

ARM Holdings out of England licenses its super power efficient ARM computing architecture to chip/systems on a chip (SoC) manufacturers such as Applied Micro, Broadcom, Cavium, Huawei, Nvidia, AMD, Samsung, and Apple. In fact, Applied Micro is now selling the “first chip to contain a software-defined network (SDN) controller on the die that will offer network services such as load balancing and ensuring service-level agreements on the chip. It’s like shoving the networking and computing vision of the Cisco Unified Computing System on a chip.” Helix, another chip, is sampling now and will be in production in 2015, will have four Helix cores running at 1.2Ghz and support fanless designs (further energy savings), AppliedMicro says.

  • Details on Cisco networking device computing architecture are difficult to gather.
  • Helix SoC from Applied Micro may be the ISR4000 Gen2?
  • Nexus 9k and 3K products, both based on Broadcom’s Trident silicon.
  • EZChip, out of Israel, purchased Tilera a few months ago. Back in 2011, Cisco invested millions in Tilera.
  • http://openvswitch.org/ is open source IOS, basically.

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