What happens if an error is detected at the lowest possible layer of the stack ISO/OSI for Ethernet?

For example, considering 100BASE-TX, it is implemented with a 4B5B coding this means that there are 16 combinations of bits are invalid. What happens if a receiver "reads" from the physical medium an invalid combination of bit, e.g. "00001"?

  • It discards that bit (invalidating the entire frame)
  • It select the "most similar" combination
  • or something else?

I know that upper layers can detect the error, e.g. the MAC layer via the FCS field, but I don't know how the transreceiver works with an error detected in the signal.

  • As described in en.wikipedia.org/wiki/4B5B 4B5C don't provide error correction, so 2-nd doesn't look like option.
    – mmv-ru
    Feb 20, 2017 at 21:07
  • @mmv-ru you are right. But it seems strange to me that the physical layer simply discards the invalid bits, in that case it would provide a frame with an incorrect length to mac layer.
    – ocirocir
    Feb 20, 2017 at 22:01
  • The physical interface will not pass on a damaged frame to the data-link layer. It discards the damaged frame, and it increases the input error count on the interface.
    – Ron Maupin
    Feb 20, 2017 at 22:26

1 Answer 1


For the specific case of 100BASE-TX and the 100Mbps MII interface: there is a receiver signal RX_ER.

The Physical Coding Sublayer (PCS) specification says: Invalid code-groups

...The PCS indicates the reception of an Invalid code-group on the MII through the use of the RX_ER signal.

The Reconciliation Sublayer and Media Independent Interface specification says: Response to RX_ER indication from MII

If, during frame reception, both RX_DV and RX_ER are asserted, the Reconciliation sublayer shall ensure that the MAC will detect a FrameCheckError in that frame.

So the PHY part indicates the error out of band, and the MAC does what it likes, as long as it ends up generating a FrameCheckError.

  • Thank you, but what happens to the invalid bit group? Will it be ignored (and consequently the frame delivered to MAC will be shorter than expected)?
    – ocirocir
    Feb 22, 2017 at 7:18
  • @RicoRico The interface is synchronous, so there won't be a gap. The 4 bits of RX data on that clock cycle are undefined.
    – richardb
    Feb 22, 2017 at 18:37

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