We recently discussed the Shannon-Harley theorem in class and compared the results between Ethernet cables to fiber optic given the same hypothetical SNR.

However, it is not clear to me how you can accurately express the capacity of a 500mhz CAT6a cable using this formula.

In order to get a capacity of 10Gbps, you would have to figure a SNR of nearly 1.5 million. Is that realistic or am I missing something regarding how this should be calculated?


You seem to be referring to 10GBASE-T. 10GBASE-R variants use 64b66b PCS encoding at 10.325 GBd.

Basically, 10GBASE-T uses PAM-16 signalling = 16 discrete voltage levels - theoretically representing four bits of information. Two consecutive signal levels are combined in a two-dimensional checkerboard DSQ128 pattern for seven bits of information. These are split over the four twisted pairs = four lanes at 800 MBd each, requiring a spectral bandwidth of only 400 MHz.

This is a simplified view, the complete encoding scheme is quite complex, check IEEE 802.3 Clause 55. The overview:

The 10GBASE-T PHY employs full duplex baseband transmission over four pairs of balanced cabling. The aggregate data rate of 10 Gb/s is achieved by transmitting 2500 Mb/s in each direction simultaneously on each wire pair, as shown in Figure 55–2. Baseband 16-level PAM signaling with a modulation rate of 800 Megasymbol per second is used on each of the wire pairs. Ethernet data and control characters are encoded at a rate of 3.125 information bits per PAM16 symbol, along with auxiliary channel bits. Two consecutively transmitted PAM16 symbols are considered as one two-dimensional (2D) symbol. The 2D symbols are selected from a constrained constellation of 128 maximally spaced 2D symbols, called DSQ128 (double square 128). After link startup, PHY frames consisting of 512 DSQ128 symbols are continuously transmitted. The DSQ128 symbols are determined by 7-bit labels, each comprising 3 uncoded bits and 4 LDPC-encoded bits. The 512 DSQ128 symbols of one PHY frame are transmitted as 4 × 256 PAM16 symbols over the four wire pairs. Data and Control symbols are embedded in a framing scheme that runs continuously after startup of the link. The modulation symbol rate of 800 Msymbols/s results in a symbol period of 1.25 ns.

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