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At the physical layer, two network interfaces of a switch run at a different clock since the reception clock is recovered from the signal and the PCS layer doesn't support any pause/empty cycles.

  • What if the source interface's frequency is lower than the destination interface's frequency? Meaning they run underflow.

  • Are they somehow unreliable? Has someone do have experience in using/developing them?

  • I know they kinda lying on the capability of the switch (SE's topic here) but do you know if these switches have a higher invalid packets rate?

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  • Even with cut-through, everything is being buffered. In the old T-carrier world, this would be a frame slip. It was rare then. It's even rarer with ethernet.
    – Ricky
    Oct 29 '21 at 6:51
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What if the source interface's frequency is lower than the destination interface's frequency?

Some slight clock skew between ingress and egress interface isn't really a problem.

Even with a high skew of .02% (Ethernet defines a maximum of ±0.01% clock tolerance), ingress loses 2 bits for every 10k transmitted bits. With standard frames, that's a maximum 2.4 bits. Given that you can only start forwarding after having received preamble, SFD, and destination MAC - 14 bytes or 112 bits in total - there's ample margin.

Even with 9k jumbos the margin's comfortable. And all this doesn't even count the switching latency which is at least a few hundred bits. Or the need to wait for L3 and L4 data if you're routing or filtering, which is in the order of 20 or 40 more bytes.

Of course, with a general difference in link speed from slower to faster (e.g. 1 Gbit/s to 10 Gbit/s), cut-through switching isn't possible.

Are they somehow unreliable?

Cut-through switching can forward frames failing FCS verification since FCS can only be checked after a frame has been completely received. However, such switches still check FCS after the fact and fail over to store-and-forward once a port exceeds a certain ingress error rate. Note that the FCS is always checked at the next L3 node, so all that defective forwarding causes is a waste of bandwidth.

I know they kinda lying on the capability of the switch (SE's topic here) but do you know if these switches have a higher invalid packets rate?

Don't get the lying bit, but CT switches don't increase the end-to-end error rate. There are quite a few ways to build a switch, so the exact implications depend on a given device.

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  • Thank you for doing the math for me. IEEE802.3 says +/-0.01%, that means if one interface is -0.01% and the other is 0.01%, there are 0.02% of difference. A standard frame is 1500B=12Kb, ingress looses about 2bits per frame. It confirms what you say. How did you get 12bits?
    – Alexis
    Oct 28 '21 at 19:29
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    That's actually true - very observant! But you're forgetting about switch latency which at least doubles the margin. Also, switches are usually clock masters, so there's no skew between ports (unless two switches are linked to each other but then again, switches are likely keeping better clock tolerances than .01%).
    – Zac67
    Oct 28 '21 at 19:35
  • It's actually 1.2 bits for a maximum frame, I messed up the order of magnitude - thx!
    – Zac67
    Oct 28 '21 at 19:39
  • What do you mean by clock master? Each interface is a clock master for the TX, all the RX are recovered (even though for a unique interface only, TX's clock can be sync'd with the RX's clock). The switch can have the same TX clock for all the interfaces nevertheless all the RX clocks are different and require a CDC. Anyway, I was too lazy to do the simple math, having done it by myself would've saved a question :) Thanks again for updating your answer!
    – Alexis
    Oct 29 '21 at 6:47
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    The TP variants starting with 1000BASE-T use a clock master/slave scheme (for the echo cancelling to work). Of course, the transmitter's clock is recovered by the receiver, but one clock is slaved to the other. Of course, that isn't valid fiber or DAC links.
    – Zac67
    Oct 29 '21 at 8:09

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