What if the source interface's frequency is lower than the destination interface's frequency?
Some slight clock skew between ingress and egress interface isn't really a problem.
Even with a high skew of .02% (Ethernet defines a maximum of ±0.01% clock tolerance), ingress loses 2 bits for every 10k transmitted bits. With standard frames, that's a maximum 2.4 bits. Given that you can only start forwarding after having received preamble, SFD, and destination MAC - 14 bytes or 112 bits in total - there's ample margin.
Even with 9k jumbos the margin's comfortable. And all this doesn't even count the switching latency which is at least a few hundred bits. Or the need to wait for L3 and L4 data if you're routing or filtering, which is in the order of 20 or 40 more bytes.
Of course, with a general difference in link speed from slower to faster (e.g. 1 Gbit/s to 10 Gbit/s), cut-through switching isn't possible.
Are they somehow unreliable?
Cut-through switching can forward frames failing FCS verification since FCS can only be checked after a frame has been completely received. However, such switches still check FCS after the fact and fail over to store-and-forward once a port exceeds a certain ingress error rate. Note that the FCS is always checked at the next L3 node, so all that defective forwarding causes is a waste of bandwidth.
I know they kinda lying on the capability of the switch (SE's topic here) but do you know if these switches have a higher invalid packets rate?
Don't get the lying bit, but CT switches don't increase the end-to-end error rate. There are quite a few ways to build a switch, so the exact implications depend on a given device.