Electronic Engineer and self-employed consultant, Physics degree, working in VHDL, Verilog, and C++, primarily in FPGA and ASIC design. I've written two compilers, including one which generates Verilog (9-pass, about 50K lines of C++). I'll add VHDL output if/when I get some spare time. I also have experience in SystemC and Specman/'e'.
Always looking for new opportunities - mail me if you want to discuss anything; I'm on
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Last seen Dec 3 '18 at 21:29