Timeline for Store and forward latency
Current License: CC BY-SA 3.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 1, 2016 at 17:49 | comment | added | Ricky | Buffer space, cost-port matrix availability, pause frames, cpu load, etc. | |
| Apr 1, 2016 at 7:41 | comment | added | user3523954 | By contention you mean that on the "out port side" there are no available buffers? OR, the switch is busy doing store and forward for the other pairs of in/out ports as well? | |
| Mar 31, 2016 at 20:37 | history | answered | Ricky | CC BY-SA 3.0 |